IBM日前宣布，公司研发出了一种垂直方向上以堆叠方式连接不同芯片的技术，这种称为“through-silicon vias”的技术可以大大减少不同芯片之前（如处理器和内存）的距离，从而加速数据的传输，并节省产品的功耗。
在IBM公司的方案中，两个芯片将被上下堆叠在一起，两者之间的距离只有几微米。这个距离将被硅填充，其中有“竖井”，里边是作为导线的金属。这样，两个芯片之间将被垂直的金属实现数据传输，距离大大缩短。 IBM的这项突破使得芯片的布局从传统的2-D并排排列发展至更先进的3-D堆叠，这样可让器件封装更加紧凑，显著减小芯片总的封装尺寸，并能够加速数据在不同功能的芯片之间的传输。
“这项突破是IBM十多年来（在该领域）先驱性研究的结果。”IBM半导体研发中心副总裁Lisa Su表示，“它使我们能够将3-D芯片从实验室带入晶圆厂（from lab to the fab），付诸多种实际应用。”
BM公司表示，通过这种垂直堆叠的技术，芯片之间的数据传输距离与2-D芯片相比缩
短了一千多倍，导线的数量则是增加了一百多倍。
IBM目前已在自身的生产线上运用该项技术制造芯片，并称可在今年下半年向客户提供样品，2008年实现量产。据悉，这一技术最先将被用于无线通信中的无线局域网功率放大器芯片以及手机芯片当中。此外，该技术还可用于IBM的高性能服务器和超级计算机使用的芯片中。
In its quest for new materials and architectures to extend Moore’s Law, Armonk, N.Y.-based technology giant IBM today detailed what it is calling a breakthrough in chip-stacking manufacturing technology that paves the way for three-dimensional (3-D) chips that will extend Moore’s Law beyond expected limits.
The technology is called “through-silicon vias,” and is meant to allow different chip components to be packaged closer together for faster, smaller and lower-power systems.
IBM said this breakthrough allows the move from horizontal 2-D chip layouts to 3-D chip stacking, which takes chips and memory devices which traditionally sit side-by-side on a silicon wafer and stacks them on top of one another, resulting in a compact sandwich of components aimed at reducing the size of the overall chip package and boosting data speed between functions on the chip.
Lisa Su, VP of semiconductor R&D at IBM noted that the breakthrough is a result of more than a decade of pioneering research and allows the move to 3-D chips from the 'lab to the fab' across a range of applications.
IBM said its method eliminates the need for long-metal wires that connect today’s 2-D chips, instead relying on through-silicon vias, which are essentially vertical connections etched through the silicon wafer