IC Packaging design Optimization for Test and Assembly
One way EDA Vendors are thinking ahead in IC packaging automation is by supplying program interaction between the designer for 2D and 3D design environments. This new design approach offers automated functionality to fully support advanced build-up substrate design technologies with 3D-pattern viewing, giving designers a sense of design in virtual-reality.
By Les Ammann, Zuken USA
As semiconductor devices become significantly mor
e complex, electronics designers are challenged to fully harness their computing power. Package design at the first interconnect level has a major impact on device performance and functionality. At the same time, electronic equipment designers are shrinking products, increasing complexity, and setting higher expectations for performance. To meet these demands, package technology must deliver higher lead counts, reduced pitch, reduced footprint area and significant overall volume reduction. This places unprecedented demands on the skills of package designers and the tools they use.
That being said, you'd think that high lead count and volume reduction were the largest challenges facing package designers today. Not exactly, recently after speaking with many advanced IC package designers I found three main points of concern regarding design automation. The first concern is the current state of package design software available, combined with the direction that design automation is going. Some feel design tool vendors today are not actively anticipating the needs for advancing future technologies. Specific automation needs such as an "all embedded" environment including layout, any-angle multi-layer auto-routing and analysis should be encompassed within an easy-flow menu structure. The second point of concern is the existing design flow between design departments and manufacturing. This communication breakdown flow needs to be addressed by supplying package feasibility up-f